Technical Field
This disclosure relates to integrated circuit devices, and more specifically, to forming a faceted structure in an integrated circuit by a self-limiting etch.
Background of the Related Art
As the dimensions of modern integrated circuitry in semiconductor chips continue to shrink, conventional lithography is increasingly challenged to make thinner and thinner structures. Some structures within the integrated circuitry are optimally thinner than the remainder of the structures, and so, if the semiconductor processes are performing at the current limitations of the lithography for most of the structures, the processes are particularly challenged to make some selected structures thinner than the remainder of the structures.
Fuses are utilized within integrated circuit devices for a variety of purposes, such as to program certain functionality into the device or to enable or disable various devices within the circuit device. Such fuse structures can make or break electrical connections (such as in physically destroyable fuses or anti-fuses). If the fuse structure is the same thickness as other device structures, the current needed to burn the fuse out can be undesirably high and can damage other devices. However, since it is desirable to make integrated circuits at whatever the current limits of lithography may be with the prior art processes it is difficult to make the fuse structure thinner than other device features.
Thus, it is desirable to provide processes which can be used to make improved fuse structures for integrated circuitry.